System 09 - VHDL 6809 System On a Chip
Please note that the URL of this web site may soon be changing
Please bookmark http://members.optusnet.com.au/jekent/system09/
3. Revision Log
4. Mailing List
5. To Do List
1. IntroductionSystem09 is an FPGA implementation of a 6809 instruction set compatible system on a chip. It is has a memory map that is similar to the old SWTPc 6809 system however also includes a number of new peripherals depending on the features available on the FPGA board. Documentation for the old SWTPc 6809 can be found on Michael Holley's web site http://www.swtpc.com/
System09 has been implemented on a number of Xilinx Spartan 2, 3 and 3E FPGA boards, and will hopefully soon be implemented on Altera Cyclone 2 Terasic FPGA boards.
System09 includes a 2KByte Sys09Bug monitor program that allows you to load and save programs from memory using Motorola S1 format, modify and dump memory. It is capable of running the Flex 9 operating system using a Compact Flash card, or a RAM disk depending on the FPGA board used.
The system includes the following (dependant to some extent on the board used):
- 6809 instruction compatible CPU
- Dynamic Address Translation registers capable of accessing 1MByte of RAM
- Sys09bug Monitor program
- 6850 compatible ACIA/UART
- PS/2 Keyboard interface
- Text based 80 x 25 character VDU with chunky graphics
- Simple 8 bit timer
- Parallel I/O port
- Hardware breakpoint / Trap for debug purposes.
- IDE Compact Flash interface (if available on the FPGA board)
The FPGA boards supported or to be supported soon include:
- BurchED B3 XC2S200 Spartan 2
- BurchED B5-X300 XC2S300 Spartan 2
- Digilent XC3S200 & XC3S1000 Spartan 3 Starter boards
- Digilent XC3S500E Spartan 3E starter board (limited memory)
- XESS XSA-3S100 with XST-3.0 carrier
- Terasic DE1 (hopefully soon)
- Terasic DE2-70 (hopefully soon)
2. Downloading System09
The latest version of System09 can be downloaded from the http://opencores.org web site using SVN or as System09.tar.gz. You may have to register with http://opencores.org/ to be able to download the files.
2.1 Directory Structure
The idea is that a new directory can be created for each new FPGA board implementations and vendor specific components such as block RAM can go in a separate folder. Currently I have folders for 4K Bit Spartan 2 block RAM/ROMs and for 16K Bit Spartan3/3E Block RAM/ROMs.
- Spartan2 (RAM & ROMS)
- Spartan3 (RAMS & ROMS)
- System09_BurchED_B3 (project files)
- System09_BurchED_B5-X300 (project files)
- System09_Digilent_3S200 (project files)
- System09_Digilent_3S500E (project files)
- System09_Xess_XSA-3S1000 (project files)
- VHDL (Common IP Cores)
3. Revision Log
I kept a log of changes as System09 was developed:
System09 Revision Log
4. Mailing List
A discussion mailing has been set up for System09 users to exchange ideas:
Many thanks go to Hans for setting it up for me.
5. To Do List
Things need to be done to System09 as of 22nd September 2010
- Convert System09 bus to wishbone
- Document components
- Upgrade 6809 to 6309
- Standardize on I/O port addressing
- Add LCD Display Interface
- Add 32 x 32 bit integer multiplier
- Make standard CF & RAM disk images for Flex9
- Implement on Altera (Terasic DE1, DE2, DE2-70)
- Port NitrOS9 level II to System09
- Implement FD179X Floppy Disk Controller interface
- Implement 6844 DMA controller
- Implement 6840 PTM Programmable Timer Module
- Implement Cache for XESS XSA-3S1000
- Implement Dual Core & Quad Core 6809
- SDRAM controller for Digilent Spartan 3E500 Starter board
- Rewrite 6845 CRT Controller
- Priority Interrupt Controller
6. 6809 Software for System09
I'm currently attempting to clean up the System09 design. You may need to get in and mess with the software to get it to work with the current board implementations.
motasm.zip - Motorola 68xx cross assemblers written in C
AS09_DWC_211.zip - Improved 6809 cross assembler by Don Coates.
S1 Dump of Flex9
S1 Dump of XBasic
Flex9sys.zip - Disk images, RAM disk down-loader and Flex9 binary (may require modification)
http://www.noicedebugger.com/ - NOICE Debugger by John Hartman
NOICE_2006-07-04.zip - NOICE ROMS for System09 (with permission from John Hartman)
John Hartman has kindly made the NOICE debugger for the 6309/6809 free if you e-mail him a description of what you are doing with a 6809 (in homage to a great processor).
http://www.oddchange.com/gcc6809/ - C Compiler for the 6809 by Brian C. Dominy
ADM3A_2006-07-16.zip - ADM3A terminal emulator for System09 written in gcc6809.
The ADM3A terminal emulator has been compiled using gcc6809 version 3.4.5 (?) running under cygwin. The version of gcc6809 I was given had problems with the frame pointer so it was necessary to use the "-fomit-frame-pointer" on the compiler. I believe the problem is now fixed or will be fixed shortly (as of 16th July 2006). The ADM3A terminal emulator needs some start-up assembler code to initialise the stack pointer before calling main(). The entry point is "_startup". You will need to look up the address in the ".map" file or use NOICE and "Play" the ".NOI" file and then look up the label. Note that you cannot single step the ADM3A terminal emulator in NOICE as it shares the serial port in system09 and will crash NOICE. You can however enter text through the NOICE command window when the terminal emulator is running.
7. System09 Memory Map:
This is the memory map I have attempted to maintain for different board implementations. I have tried to maintain consistency with the SWTPc (South West Technical Products Computer) memory map although some FPGA board implementations do not support sufficient memory or have the appropriate I/O interface available.
$00000 - $FFFFF RAM (Overlayed by I/O & ROM at $XEXXX & $XFXXX) $XE000 - $XE7FF(1) I/O Space $XE800 - $XEFFF(1) Reserved for External Bus or Memory Mapped VDU $XF000 - $XF7FF(1) RAM for Monitor ROM Extension.
Also used for the DMAF-2 Floppy Disk Controller on the SWTPc.
$XF800 - $XFEFF(1) Sys09bug Monitor ROM $XFF00 - $XFFFF(2) Monitor ROM / Dynamic Address Translation Registers
(1) Physical Address bits PA[19..16] generated by the DAT are not decoded
(2) Logical Address Range $FF00 to $FFFF is not mapped through the DAT.
7.1 Dynamic Address Translation ($FFXX):
The Dynamic Address Translation Registers extends the addressing range of the 6809 to 1MByte by mapping the top 4 address lines of the 6809 through a 16 register 8 bit look up table to generate 8 Physical Address lines. This allows any 4KByte memory block in the 6809 Logical Address range to be mapped into any 4K memory block of the 1MByte Physical Address range. The bottom 4 Physical Address lines are inverted out of the DAT to be compatible with the SWTPc MP-09 CPU Board. Also the address range from $E000 to $FFFF is not decoded using the top 4 Physical Address lines. Address range $FF00 to $FFFF is not mapped through the DAT. A read performed in this range reads the monitor ROM, a write sets the DAT registers, so the top 256 bytes of the monitor ROM can be used to configure the DAT on reset.
$FFF0 Memory Page $0XXX $FFF1 Memory Page $1XXX $FFF2 Memory Page $2XXX $FFF3 Memory Page $3XXX $FFF4 Memory Page $4XXX $FFF5 Memory Page $5XXX $FFF6 Memory Page $6XXX $FFF7 Memory Page $7XXX $FFF8 Memory Page $8XXX $FFF9 Memory Page $9XXX $FFFA Memory Page $AXXX $FFFB Memory Page $BXXX $FFFC Memory Page $CXXX $FFFD Memory Page $DXXX $FFFE Memory Page $EXXX $FFFF Memory Page $FXXX
7.1.1 DAT Register Value:
Bit Bit Bit Bit Bit Bit Bit Bit[0} PA19 PA18 PA17 PA16 PA15* PA14* PA13* PA12*
PA = Physical Address
PAxx* = Inverted Physical Address
7.2 I/O Memory Map:
The SWTPc maps I/O devices form $E000 to $E0AF in 16 byte slots. I have attempted to maintain some degree of compatibility with the SWTPc convention. Not all FPGA board implementation have all the peripherals implemented. By maintaining a consistent memory map, I/O drivers can be easily used on different board implementations with out the need to redefine I/O addresses.
$E00X ACIA (UART) $E01X Reserved for Floppy Disk Controller (SWTPc) $E02X PS/2 Keyboard $E03X 80 x 25 character VDU $E04X Reserved for MP-T Timer (SWTPc) $E05X Timer $E06X Hardware Breakpoint / Bus Trap $E07X Parallel I/O port $E08X Reserved for 6821 Printer/Counter PIA (SWTPc) $E09X Reserved for 6840 Programmable Timer Module (SWTPc) $E0AX Reserved $E0BX Reserved $E0CX Reserved $E0DX Reserved $E0EX Reserved $E0FX Reserved
7.2.1 ACIA Registers ($E00X)
$E000 Command / Status Register $E001 TX / RX Data Register
126.96.36.199 ACIA Status Register ($E000 Read)
Bit Bit Bit Bit Bit Bit Bit Bit[0} IRQ PErr OErr FErr CTS DCD TxBE RxDR
Bit - IRQ - Interrupt request
Bit - PErr - Receive Parity error (parity bit does not match)
Bit - OErr - Receive Overrun error (new character received before last read)
Bit - FErr - Receive Framing Error (bad stop bit)
Bit - CTS - Clear To Send level
Bit - DCD - Data Carrier Detect (lost modem carrier)
Bit - TxBE - Transmit Buffer Empty (ready to accept next transmit character)
Bit - RxDR - Receive Data Ready (character received)
188.8.131.52 ACIA Control Register ($E000 Write)
Bit Bit Bit Bit Bit Bit Bit Bit[0} RxIEnb TxCtl(1) TxCtl(0) WdFmt(2) WdFmt(1) WdFmt(0) BdCtl(1) BdCtl(0)
Bit - RxIEnb
-- 0 - Rx Interrupt disabled
-- 1 - Rx Interrupt enabled
Bits[6..5] - TxCtl
-- 0 1 - Tx Interrupt Enable
-- 1 0 - RTS high
Bits[4..2] - WdFmt
-- 0 0 0 - 7 data, even parity, 2 stop
-- 0 0 1 - 7 data, odd parity, 2 stop
-- 0 1 0 - 7 data, even parity, 1 stop
-- 0 1 1 - 7 data, odd parity, 1 stop
-- 1 0 0 - 8 data, no parity, 2 stop
-- 1 0 1 - 8 data, no parity, 1 stop
-- 1 1 0 - 8 data, even parity, 1 stop
-- 1 1 1 - 8 data, odd parity, 1 stop
Bits[1..0] - BdCtl
-- 0 0 - Baud Clk divide by 1
-- 0 1 - Baud Clk divide by 16
-- 1 0 - Baud Clk divide by 64
-- 1 1 - Reset
7.2.2 PS/2 Keyboard Registers ($E02X):
$E020 Control / Status Register $E021 Tx / Rx Data Register
184.108.40.206 Keyboard Control Register ($E020 Write)
Bit Bit Bit Bit Bit Bit Bit Bit[0} RxIE CRB6 - - - - - -
Bit - RxIE - Receive Interrupt Enable
Bit - CRB6 - Control Register Bit 6 (no function)
Bit[5..0] - Undefined
220.127.116.11 Keyboard Status Register ($E020 Read)
Bit Bit Bit Bit Bit Bit Bit Bit[0} RxIRQ CRB 6 TxErr ShftOn KeyRel KeyExt TxDE RxDR
Bit - RxIRQ - Receive Interrupt Request
Bit - CRB6 - Control Register Bit 6 (no function)
Bit - TxErr - Transmit Error - No keyboard detected
Bit - ShftOn - Keyboard Shift On
Bit - KeyRel - Key Released
Bit - KeyExt - Key Extended
Bit - TxDE - Transmit Data Empty
Bit - RxDR - Receive Data Ready (Valid data in receive register)
7.2.3 VDU Registers ($E03X):
The VDU is a text based display with 2K bytes of text buffer memory and 2K bytes of character attribute memory designed to run with a high resolution PC video monitor.
The VDU is permanently configured for 80 characters across by 25 characters down. It supports 8 foreground colours and 8 background colours and also supports alternating flashing characters and a chunky graphics character mode.
Pixel Clock 25 MHz Horizontal Pixels / Character 8 Pixels Horizontal Display Characters 80 Characters Horizontal Sync Period 3.84 usec Horizontal Sync Frequency 31.25 KHz Vertical Lines / Character 16 Lines Vertical Display Characters 25 Characters Vertical Sync Pulse Period 32 usec Vertical Sync Frequency 70 Hz (approx)
Please ensure your video monitor is capable of supporting this format before using it with System09. No responsibility is taken for damage to your monitor if it does not meet these specifications (or even if it does for that matter).
A flashing cursor is displayed at the Cursor Column and Row position. The Cursor Column position must be modulo 80, and the Cursor Row position should be modulo 25. The process of writing a character to the screen is to set the Cursor Column and Row coordinate then write the Character attribute byte, then the ASCII character code to the Write Character register. The value of the Write Attribute register is preserved so writing to the Write Character register will use what ever value was previously stored in the Write Attribute register.
The display can be scrolled up or down using the Row Display Offset. The Row Display Offset sets the starting address in the text buffer and attribute buffer memory. When the display is scrolled up or down, the Row Display Offset should be rounded modulo 25. The Cursor Column and Row position is relative to the screen position with the 0,0 coordinate being at the top left of the screen.
$E030 Write Character (at cursor) $E031 Write Attribute (colour - RGB foreground & background) $E032 Cursor column position (0-79) $E033 Cursor row position (0-24) $E034 Row Display Offset (0-24)
18.104.22.168 VDU Attribute Register ($E031):
Bit Bit Bit Bit Bit Bit Bit Bit[0} Graphics BG Blue BG Green BG Red Blink FG Blue FG Green FGRed
I'm not sure this is 100% accurate but you get the idea.
In graphics mode, (Graphics bit set) characters represent a 8 pixel graphics characters and are displayed as follows:
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
7.2.4 Timer Registers ($E05X):
$E050 Read - Down Count $E050 Write - Preset Count $E051 Read - Status $E051 Write - Control
22.214.171.124 Timer Control RegisterBit - interrupt enable
Bit[6..2] - undefined
Bit - mode (0 = counter, 1 = timer)
Bit - counter enable
126.96.36.199 Timer Status registerBit - interrupt flag
Bit - timer output
Bit[5..0] - undefined
7.2.5 Hardware Breakpoint / Bus Trap Registers ($E06X):
$E060 Address Comparator High Byte A[15..8] $E061 Address Comparator Low Byte A[7..0] $E062 Data Comparator D[7..0] $E063 Control Comparator VMA, R/W $E064 Address Qualifier High Byte A[15..8] $E065 Address Qualifier Low Byte A[7..0] $E066 Data Qualifier D[7..0] $E067 Control Qualifier VMA, R/W
Address, Data and Control signals must match in the Comparator registers
Matches are qualified by setting a bit in the Qualifier registers
188.8.131.52 Trap Control Comparator (write)Bit - Match polarity 1=match 0=mismatch
Bit[6..2] - undefined
Bit - VMA
Bit - R/W 1=read 0=write
184.108.40.206 Trap Control Qualifier (write)Bit - Interrupt Enable
Bit[6..2] - undefined
Bit - VMA 1=valid 0=don't care
Bit - R/W 1=valid 0=don't care
220.127.116.11 Trap Control Qualifier (read)Bit - Match flag
7.2.6 Parallel I/O Port Registers ($E07X):
$E070 Data I/O Register A $E071 Data I/O Register B $E072 Data Direction Register A $E073 Data Direction Register B
7.3 I/O Peripheral Bus Map:
The XESS XST-3.0 carrier board allows for an IDE bus connection, Ethernet chip connection and two expansion slot connections via a common 16 bit data bus. Each slot in the Peripheral Bus decoding occupies 64 bytes and there are 4 slots making a 256 byte addressing range. I have attempted to maintain the same memory map across each board implementation, although many boards do not have an Ethernet device and some boards do not have an IDE or CF interface.
Since System09 is only an 8 bit microcomputer, a latching system has been set up so that 16 bit reads and writes may be performed. Note that the 6809 uses big endian addressing so that the first byte read or written is the high order byte.
On a 16 bit read the high order even byte read reads the device and the lower byte of the 16 bit read from the device is latched and read on the odd order byte access to the peripheral bus. On a 16 bit write the high order byte on the even address write is latched and on the odd order lower byte write, both the latched high byte and written low byte is written to the device as a 16 bit word.
$E100 - $E13F IDE / Compact Flash interface $E140 - $E17F Ethernet Controller Interface $E180 - $E1BF Expansion Slot 1 Interface $E1C- - $E1FF Expansion Slot 2 Interface
7.3.1 IDE / Compact Flash Registers ($E10X):
$E100 Data Register $E102 Error/Feature Register $E104 Sector Count Register $E106 Sector Number Register / LBA[7..0] $E108 Cylinder Low Register / LBA[15..8] $E10A Cylinder High Register / LBA[23..16] $E10B Head Register / LBA [??..24] $E10C Command / Status Register
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